EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 608
EP1S10F484I6
Manufacturer Part Number
EP1S10F484I6
Description
IC STRATIX FPGA 10K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S10F484I6
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
335
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
10570
# I/os (max)
335
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
10570
Ram Bits
920448
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S10F484I6
Manufacturer:
ALTERA
Quantity:
3 000
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Finite Impulse Response (FIR) Filters
Figure 7–17. Implementation of the Polyphase Decimation Filter (D=4)
Notes to
(1)
(2)
(3)
7–30
Stratix Device Handbook, Volume 2
Clock input
(1x clock)
Data input
The 1
The 4
optional registers in the DSP block (see
To increase the DSP block performance, include the pipeline, and output registers. See
the details.
x(n)
x x
Figure
clock feeds the shift register for the data, the input registers for both the data and filter coefficients, the other
clock feeds the register after the accumulator block.
D
D
D
D
D
D
D
7–17:
Q
Q
Q
Q
Q
Q
Q
PLL
D
D
D
D
4x clock
1x clock
D
D
Q
Q
Q
Q
Q
Q
coefficients
Note
Filter
ROM
ROM
ROM
(3)), and the accumulator block.
D
D
D
D
D
D
D
D
Q
Q
Q
Q
Q
Q
Q
Q
Note (2)
Notes
(1), (2),
DSP block
Figure 7–3 on page 7–8
(3)
Note (1)
Altera Corporation
September 2004
D
Filter output
Q
y(n)
for
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