EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 458

IC STRATIX FPGA 10K LE 484-FBGA

EP1S10F484I6

Manufacturer Part Number
EP1S10F484I6
Description
IC STRATIX FPGA 10K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheets

Specifications of EP1S10F484I6

Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
335
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
10570
# I/os (max)
335
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
10570
Ram Bits
920448
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant

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I/O Pad Placement Guidelines
I/O Pad
Placement
Guidelines
4–30
Stratix Device Handbook, Volume 2
Differential termination for Stratix devices is supported for the left and
right I/O banks. Differential termination for Stratix GX devices is
supported for the left, source-synchronous I/O bank. Some of the clock
input pins are in the top and bottom I/O banks, which do not support
differential termination. Clock pins CLK[1,3,8,10] support differential
on-chip termination. Clock pins CLK[0,2,9,11], CLK[4-7], and CLK[12-15]
do not support differential on-chip termination.
Transceiver Termination
Stratix GX devices feature built-in on-chip termination within the
transceiver at both the transmit and receive buffers. This termination
improves signal integrity and provides support for the 1.5-V PCML I/O
standard.
This section provides pad placement guidelines for the programmable
I/O standards supported by Stratix and Stratix GX devices and includes
essential information for designing systems using the devices' selectable
I/O capabilities. These guidelines will reduce noise problems so that
FPGA devices can maintain an acceptable noise level on the line from the
V
each bank, these noise issues do not have any effect when crossing bank
boundaries and these guidelines do not apply. Although pad placement
rules need not be considered between I/O banks, some rules must be
considered if you are using a VREF signal in a PLLOUT bank. Note that the
signals in the PLLOUT banks share the V
banks and, therefore, must adhere to the V
Pad Placement
Differential Pad Placement Guidelines
To avoid cross coupling and maintain an acceptable noise level on the
V
pads in relation to differential pads. Use the following guidelines for
placing single-ended pads with respect to differential pads in Stratix
devices. These guidelines apply for LVDS, HyperTransport technology,
LVPECL, and PCML I/O standards. The differential pad placement
guidelines do not apply for differential HSTL and differential SSTL
output clocks since each differential output clock is essentially
implemented using two single-ended output buffers. These rules do not
apply to differential HSTL input clocks either even though the dedicated
input buffers are used. However, both differential HSTL and differential
SSTL output standards must adhere to the single-ended (VREF) pad
placement restrictions discussed in
CCIO
CCIO
supply, there are restrictions on the placement of single-ended I/O
supply. Since Altera FPGAs require that a separate V
Guidelines”.
“VREF Pad Placement
REF
REF
supply with neighboring I/O
rules discussed in
Altera Corporation
Guidelines”.
CCIO
June 2006
power
“VREF

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