EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 478
EP1S10F484I6
Manufacturer Part Number
EP1S10F484I6
Description
IC STRATIX FPGA 10K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S10F484I6
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
335
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
10570
# I/os (max)
335
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
10570
Ram Bits
920448
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S10F484I6
Manufacturer:
ALTERA
Quantity:
3 000
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Principles of SERDES Operation
Principles of
SERDES
Operation
5–6
Stratix Device Handbook, Volume 2
signaling, you can configure them as any of the other supported I/O
standards. DDRIO capabilities are detailed in
Differential Signaling”
Stratix devices support source-synchronous differential signaling up to
840 Mbps. Serial data is transmitted and received along with a low-
frequency clock. The PLL can multiply the incoming low-frequency clock
by a factor of 1 to 10. The SERDES factor J can be 4, 7, 8, or 10 and does not
have to equal the clock multiplication value.
possible by bypassing the SERDES; it is explained in
DDR Differential Interface Review”
On the receiver side, the high-frequency clock generated by the PLL shifts
the serial data through a shift register (also called deserializer). The
parallel data is clocked out to the logic array synchronized with the low-
frequency clock. On the transmitter side, the parallel data from the logic
array is first clocked into a parallel-in, serial-out shift register
synchronized with the low-frequency clock and then transmitted out by
the output buffers.
There are four dedicated fast PLLs in EP1S10 to EP1S25 devices, and eight
in EP1S30 to EP1S80 devices. These PLLs are used for the SERDES
operations as well as general-purpose use.
The differential channels and the high-speed PLL layout in Stratix
devices are described in the
section on
Note to
(1)
Left
Right
Top
Bottom
Device Side
Table 5–1. I/O Pin Locations on Each Side of Stratix Devices
Device sides are relative to pin A1 in the upper left corner of the device (top view
of the package).
Table
page
(1)
5–1:
5–16.
Differential Input
on
v
v
page
“Differential I/O Interface & Fast PLLs”
5–42.
on
page
Differential Output
5–42.
×
“SERDES Bypass DDR
1 and
v
v
×
“SERDES Bypass
2 operation is also
Altera Corporation
DDRIO
July 2005
v
v
v
v
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