EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 543

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Figure 5–44. LVDS x2 Mode Schematic Using DDR I/O Circuitry
Altera Corporation
July 2005
rx_inclk
RXp
RXn
datain[0]
inclock
inclock
RX_PLL
DDIO In
dataout_h[0]
dataout_l[0]
The transmitter output clock requires extra DDR output circuitry that has
the input high and input low connected to V
output clock frequency is the same as the input frequency of the DDR
output circuitry.
Other Modes
For other modes, you can still to use the DDR circuitry for better
frequency performance. You can use either the LEs or the M512 RAM
block for the deserialization.
M512 RAM Block as Serializer/Deserializer Interface
In addition to using the DDR circuitry and the M512 RAM block, you
need two extra counters per memory block to provide the address for the
memory: a fast counter powering up at 0 and a slow counter powering up
at 2. The M512 RAM block is configured as a simple dual-port memory
block, where the read enable and the write enable signals are always tied
high.
bypass receiver and SERDES bypass transmitter, respectively.
/1 clock1
/2 clock0
Figures 5–45
Custom Logic
and
High-Speed Differential I/O Interfaces in Stratix Devices
5–46
show the block diagram for the SERDES
GND
V
CC
datain_h[0]
datain_l[0]
outclock
datain_h[0]
datain_l[0]
outclock
Stratix Device Handbook, Volume 2
DDIO Out
DDIO Out
CC
and GND respectively. The
dataout[0]
dataout[0]
TXp
TXn
tx_outclk
5–71