EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 399

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Altera Corporation
June 2006
Read & Write Operations
When reading from the DDR SDRAM, the DQS signal coming into the
Stratix and Stratix GX device is edge-aligned with the DQ pins. The
dedicated circuitry center-aligns the DQS signal with respect to the DQ
signals and the shifted DQS bus drives the clock input of the DDR input
registers. The DDR input registers bring the data from the DQ signals to
the device. The system clock clocks the DQS output enable and output
paths. The -90° shifted clock clocks the DQ output enable and output
paths.
during a burst-of-two read. It shows where the DQS signal is
center-aligned in the IOE.
Figure 3–1. Example of Where a DQS Signal is Center-Aligned in the IOE
When writing to the DDR SDRAM, the DQS signal must be center-
aligned with the DQ pins. Two PLL outputs are needed to generate the
DQS signal and to clock the DQ pins. The DQS are clocked by the 0°
phase-shift PLL output, while the DQ pins are clocked by the -90° phase-
shifted PLL output.
during a DDR SDRAM burst-of-two write.
Figure 3–2. DQ & DQS Relationship During a Burst-of-Two Write
IOE registers
IOE registers
DQS at DQ
FPGA Pin
FPGA Pin
DQ at DQ
FPGA Pin
FPGA Pin
DQS at
DQ at
Figure 3–1
DQS at
DQ at
External Memory Interfaces in Stratix & Stratix GX Devices
shows an example of the DQ and DQS relationship
Figure 3–2
Preamble
shows the DQS and DQ relationship
90 degree shift
Stratix Device Handbook, Volume 2
Pin to register
delay
Pin to register
delay
Postamble
3–3