EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 677
EP1S10F484I6
Manufacturer Part Number
EP1S10F484I6
Description
IC STRATIX FPGA 10K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S10F484I6
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
335
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
10570
# I/os (max)
335
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
10570
Ram Bits
920448
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S10F484I6
Manufacturer:
ALTERA
Quantity:
3 000
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Figure 9–5. Framer Transmitter Interface in Stratix & Stratix GX Devices
Altera Corporation
July 2005
Stratix & Stratix GX SFI-4 Transmitter
Stratix & Stratix GX
Logic Array
Fast PLL
8
8
Figure 9–6
interface implemented in Stratix and Stratix GX devices.
RXDATA[15..0] is received from the OC-192 SERDES on the differential
I/O pins of the Stratix or Stratix GX device. The receiver SERDES
converts the high-speed serial data to parallel. You can generate the
clocks required in the SERDES for parallel and serial data conversion
from the received RXCLK. RXCLK is inverted (phase-shifted by 180 ) to
capture received data. While normal I/O operation guarantees that data
is captured, it does not guarantee the parallelization boundary, which is
randomly determined based on the power up of both communicating
devices. The SERDES has embedded data realignment capability, which
can be used to save logic elements (LEs).
Stratix & Stratix GX SERDES
÷J
Register
Parallel
622 MHz
× W
shows the receiver block (from
Parallel-to-Serial
Register
W = 1
CH15
J = 8
CH0
Implementing SFI-4 in Stratix & Stratix GX Devices
Stratix Device Handbook, Volume 2
TXCLK_SRC
TXDATA[15]
TXDATA[0]
622 Mbps
622 MHz
622MHz
TXCLK
Figure
9–4) of the SFI-4 framer
SERDES
OC-192
9–7
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