EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 436
EP1S10F484I6
Manufacturer Part Number
EP1S10F484I6
Description
IC STRATIX FPGA 10K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S10F484I6
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
335
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
10570
# I/os (max)
335
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
10570
Ram Bits
920448
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S10F484I6
Manufacturer:
ALTERA
Quantity:
3 000
- Current page: 436 of 864
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Stratix & Stratix GX I/O Standards
4–8
Stratix Device Handbook, Volume 2
3.3-V 2× AGP - Intel Corporation Accelerated Graphics Port
Interface Specification 2.0
The 2 AGP I/O standard is a voltage-referenced, single-ended standard
used for 3.3-V graphics applications. The 2 AGP input standard
specifies an input voltage range of – 0.5V V
standard does not require board terminations. Stratix and Stratix GX
devices support both input and output levels.
GTL - EIA/JEDEC Standard EIA/JESD8-3
The GTL I/O standard is a low-level, high-speed back plane standard
used for a wide range of applications from ASICs and processors to
interface logic devices. The GTL standard defines the DC interface
parameters for digital circuits operating from power supplies of 2.5, 3.3,
and 5.0 V. The GTL standard is an open-drain standard, and Stratix and
Stratix GX devices support a 2.5- or 3.3-V V
GTL requires a 0.8-V V
Figure
levels.
Figure 4–4. GTL Termination
GTL+
The GTL+ I/O standard is used for high-speed back plane drivers and
Pentium processor interfaces. The GTL+ standard defines the DC
interface parameters for digital circuits operating from power supplies of
2.5, 3.3, and 5.0 V. The GTL+ standard is an open-drain standard, and
Stratix and Stratix GX devices support a 2.5- or 3.3-V V
standard. GTL+ requires a 1.0-V V
1.5-V V
input and output levels.
4–4). Stratix and Stratix GX devices support both input and output
TT
(see
Output Buffer
Figure
V
4–5). Stratix and Stratix GX devices support both
TT
REF
= 1.2 V
V
and open-drain outputs with a 1.2-V V
50 Ω
REF
Z = 50 Ω
= 0.8 V
REF
V
TT
and open-drain outputs with a
= 1.2 V
50 Ω
CCIO
I
V
to meet this standard.
CCIO
Input Buffer
+ 0.5V. The 2 AGP
Altera Corporation
CCIO
to meet this
June 2006
TT
(see
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