EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 517

IC STRATIX FPGA 10K LE 484-FBGA

EP1S10F484I6

Manufacturer Part Number
EP1S10F484I6
Description
IC STRATIX FPGA 10K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheets

Specifications of EP1S10F484I6

Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
335
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
10570
# I/os (max)
335
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
10570
Ram Bits
920448
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant

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Figure 5–31.
High-Speed
Interface Pin
Locations
Altera Corporation
July 2005
×
2 Data Rate Transmitter Channel with Serialization Factor of 8
Stratix
Logic
Array
PLL
D0, D2,
D1, D3,
×1
D4, D6
D5, D7
×4
×1
Figure 5–30.
Stratix high-speed interface pins are located at the edge of the package to
limit the possible mismatch between a pair of high-speed signals. Stratix
devices have eight programmable I/O banks.
pins and their location relative to the package.
datain_h
outclock
datain_l
dataout
Register
Register
XX
XX
Shift
Shift
×
2 Timing Relation between Parallel Data & Clock
XX
B0
A0
High-Speed Differential I/O Interfaces in Stratix Devices
A0
DDR IOE
B0
DFF
DFF
B1
A1
A1
Stratix Device Handbook, Volume 2
B1
Figure 5–32
B2
A2
A2
dataout
inclock
B2
shows the I/O
B3
A3
A3
5–45

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