EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 427

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Altera Corporation
Chapter
5
September 2004,
November 2003,
April 2004, v3.0
July 2005, v3.2
July 2003, v2.0
October 2003,
Date/Version
v3.1
v2.2
v2.1
Updated
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Updated Note 3 in
Updated
Updated
Updated description of
page
Updated Note 5 in
Updated Notes 2, 5, and 7 in
through
Added new text about spanning two I/O banks on
page
Updated notes for
Updated
“Data Alignment with Clock”
made from 90 degrees to 180 degrees.
Removed support for series and parallel on-chip
termination.
Updated the number of channels per PLL in Tables 5-10
through 5-14.
Added -8 speed grade device information, including Tables
5-7 and 5-8.
Format changes throughout Chapter.
Relaxed restriction of input pins next to differential pins for
flip chip packages in Figure 5-1, Note 5.
Wire bond package performance specification for “high”
speed channels was increased to 624 Mbps from 462 Mbps
throughout Chapter.
Updated high-speed I/O specification for J=2 in Tables 5-7
and 5-8.
Updated Tables 5-10 to 5-14 to reflect PLL cross-bank
support for high-speed differential channels at full speed.
Increased maximum output clock frequency to 462 to 500
MHz on page 5-66.
5–46.
5–60.
Table 5–14 on page
Table 5–14 on page
Table 5–7 on page
Table 5–8 on page
Table
5–7, 5–8, and 5–10.
Figure
Table 5–10 on page
Table 5–14 on page
Changes Made
“R
5–17.
D
5–58.
Differential Termination” on
section, last sentence: change
5–34.
5–36.
5–58.
Table 5–11 on page 5–56
5–54.
5–58.
Comments
I/O Standards
Section III–3