EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 651
EP1S10F484I6
Manufacturer Part Number
EP1S10F484I6
Description
IC STRATIX FPGA 10K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S10F484I6
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
335
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
10570
# I/os (max)
335
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
10570
Ram Bits
920448
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S10F484I6
Manufacturer:
ALTERA
Quantity:
3 000
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Figure 8–5. Stratix & Stratix GX Device XSBI Implementation
Altera Corporation
July 2005
Logic Array
Stratix GX
Stratix &
Data
Data
Stratix & Stratix GX PCS
Transmitter
Receiver
Implementation
The 16-bit full duplex LVDS implementation of XSBI in Stratix devices is
shown in
The source-synchronous I/O implemented in Stratix GX devices
optionally includes dynamic phase alignment (DPA). DPA automatically
and continuously tracks fluctuations caused by system variations and
self-adjusts to eliminate the phase skew between the multiplied clock and
the serial data, allowing for data rates of 1 Gbps. In non DPA mode the
I/O behaves similarly to that of the Stratix I/O. This document assumes
that DPA is disabled. However, it is simple to implement the same system
with DPA enabled to take advantage of its features. For more information
on DPA, see the Stratix GX Transceivers chapter in the Stratix GX Device
Handbook, Volume 1.
PLL2
PLL1
÷8
Transmitter
SERDES
Receiver
SERDES
÷8
Implementing 10-Gigabit Ethernet Using Stratix & Stratix GX Devices
Figure
Phase Shift
180˚
8–5.
×1
PMA_TXCLK_SRC
PMA_RXCLK
PMA_TXCLK
RX_D[15..0]
TX_D[15..0]
Stratix Device Handbook, Volume 2
PMA
Transmitter
Receiver
8–7
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