EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 467

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Altera Corporation
June 2006
Device & Pin Options
Click Device & Pin Options in the Compiler Settings dialog box to
access the I/O pin settings. For example, in the Voltage tab you can select
a default I/O standard for all pins for the targeted device. I/O pins that
do not have a specific I/O standard assignment default this standard.
Click OK when you are done setting I/O pin options to return to the
Compiler Settings dialog box.
Assign Pins
Click Assign Pins in the Compiler Settings dialog box to view the
device’s pin settings and pin assignments (see
the pin settings under Available Pins & Existing Assignments. The
listing does not include V
information for each pin includes:
■
■
■
■
■
■
■
■
Figure 4–23. Assign Pins
Number
Name
I/O Bank
I/O Standard
Type (e.g., row or column I/O and differential or control)
SignalProbe Source Name
Enabled (that is, whether SignalProbe routing is enabled or disabled
Status
Selectable I/O Standards in Stratix & Stratix GX Devices
REF
pins because they are dedicated pins. The
Stratix Device Handbook, Volume 2
Figure
4–23). You can view
4–39