EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 419
![IC STRATIX FPGA 10K LE 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP1S10F484I6
Manufacturer Part Number
EP1S10F484I6
Description
IC STRATIX FPGA 10K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S10F484I6
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
335
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
10570
# I/os (max)
335
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
10570
Ram Bits
920448
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S10F484I6
Manufacturer:
ALTERA
Quantity:
3 000
- Current page: 419 of 864
- Download datasheet (11Mb)
Figure 3–12. DQ Configuration in Stratix & Stratix GX IOE
Notes to
(1)
(2)
(3)
(4)
Altera Corporation
June 2006
Logic Array
You can use the altdq megafunction to generate the DQ signals.
The OE signal is active low, but the Quartus II software implements this as active high and automatically adds an
inverter before the OE register A
The outclock signal is phase shifted –90° from the system clock.
The shifted DQS signal must be inverted before going to the IOE. The inversion is automatic if you use the altdq
megafunction to generate the DQ signals.
Figure
3–12:
dataout_h
(4)
dataout_l
inclock (from DQS bus)
(2)
datain_h
outclock (3)
OE
datain_l
OE
during compilation.
Latch C
Q
Latch
ENA
TCH
Output Register A
Output Register B
External Memory Interfaces in Stratix & Stratix GX Devices
I
D
LA
OE Register A
DFF
DFF
DFF
D
D
D
neg_reg_out
Q
Q
Q
OE
Note (1)
O
O
Input Register A
Input Register B
Q
Q
DFF
DFF
Stratix Device Handbook, Volume 2
D
D
0
1
I
I
TRI
DQ Pin
3–23
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