EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 379
EP1S10F484I6
Manufacturer Part Number
EP1S10F484I6
Description
IC STRATIX FPGA 10K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S10F484I6
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
335
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
10570
# I/os (max)
335
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
10570
Ram Bits
920448
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S10F484I6
Manufacturer:
ALTERA
Quantity:
3 000
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Figure 2–5. Simple Dual-Port Timing Waveforms
Note to
(1)
Altera Corporation
July 2005
asynch_data_out
synch_data_out
wraddress
rdaddress
The rden signal is not available in the M-RAM block. A M-RAM block in simple dual-port mode is always reading
out the data stored at the current read address location.
wrclock
data_in
rdclock
wren
rden
Figure
doutn-2
2–5:
din-1
an-1
doutn-1
bn
an
din
M-RAM blocks have one write enable signal in simple dual-port mode. To
perform a write operation, the write enable is held high. The M-RAM
block is always enabled for read operation. If the read address and the
write address select the same address location during a write operation,
the M-RAM block output is unknown.
Figure 2–5
simple dual-port mode.
Implementing True Dual-Port Mode
M4K and M-RAM blocks offer a true dual-port mode to support any
combination of two-port operations: two reads, two writes, or one read
and one write at two different clock frequencies.
true dual-port memory configuration for TriMatrix memory.
doutn-1
doutn
a0
b0
TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices
shows timing waveforms for read and write operations in
a1
Note (1)
doutn
dout0
a2
b1
a3
Stratix Device Handbook, Volume 2
dout0
din4
a4
b2
Figure 2–6
din5
a5
shows the
b3
din6
2–11
a6
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