PEB2255H-V13 Infineon Technologies, PEB2255H-V13 Datasheet - Page 105

• Manufacturer Part Number: PEB2255H-V13
• Description: IC INTERFACE LINE 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2255H-V13

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2255H-V13; PEB2255H-V13IN

• Recovery:
Note: In long haul mode, LOS alarm is declared either if “no pulses” are detected
5.1.6
The receive jitter attenuator is placed in the receive path. The jitter attenuator meets the
requirements of PUB 62411, PUB 43802, TR-TSY 009,TR-TSY 253, TR-TSY 499 and
ITU-T I.431, G.703 and G. 824.
The internal DCO-R generates a “jitter free“ output clock which is directly dependent on
the phase difference of the incoming clock and the jitter attenuated clock. The receive
jitter attenuator can be either synchronized with the extracted receive clock RCLK or to
a 1.544 or 2.048-MHz clock provided on pin SYNC. Received data are written into the
receive elastic buffer with RCLK and are read out with SCLKR. Optionally an 8 kHz clock
is provided on pin XCLK/FSC or FSC.
The DCO-R circuitry attenuates the incoming jittered clock starting at 6 Hz jitter
frequency with 20 dB per decade fall off. Wander with a jitter frequency below 6 Hz is
passed unattenuated. The intrinsic jitter in the absence of any input jitter is < 0.02UI.
Data Sheet
haul mode (LIM0.EQON = 1) the analog LOS criteria is defined by the equalizer
status. The number N may be set via a 8 bit register PCD. The contents of the PCD
register is multiplied by 16, which results in the number of pulse periods, or better, the
time which has to suspend until the alarm has to be detected. The range therefore
results from 16 to 4096 pulse periods.
In general the recovery procedure starts after detecting a logical “one“ (digital receive
interface) or a pulse (analog receive interface) with an amplitude more than Q dB
(defined by LIM1.RIL2...0) of the nominal pulse. The value in the 8 bit register PCR
defines the number of pulses (1 to 255) to clear the LOS alarm. Additional recovery
conditions may be programmed by register LIM2.
for the period defined in PCD or the signal level drops below typically about
-35 dB of the nominal signal (“low signal level”). Additionally, the incoming
data stream is cleared, if this “low signal level” is detected in order to
generate a fixed data stream before first bit errors occur. Typically, this loss
of signal threshold is about -36 dB. Because the DS1 signal varies at 3.0V +/
- 20%, this loss of signal threshold correlates directly to the transmitted
pulse amplitude. It changes to -33 dB, if the generated maximum transmit
amplitude at the remote end is not more than 2.4V
For recovery this means, that at first the signal level has to increase and
then the pulses are counted and compared to PCR to return from LOS
indication.
Please also note, that this behavior is slightly different to FALC-LH V1.1.
Receive Jitter Attenuator (T1/J1)
105
Functional Description T1/J1
FALC-LH V1.3
PEB 2255
2000-07