PEB2255H-V13 Infineon Technologies, PEB2255H-V13 Datasheet - Page 255

• Manufacturer Part Number: PEB2255H-V13
• Description: IC INTERFACE LINE 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2255H-V13

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2255H-V13; PEB2255H-V13IN

LMFA16…
AIS16…
RA16…
API…
RSN…
RSP…
Data Sheet
Loss of Multiframe Alignment TS 16
Multiframe alignment of timeslot 16 has been lost if two consecutive
multiframe pattern are not detected or if in 16 consecutive timeslot 16
all bits are reset.
If register IPC.SCI is high this interrupt status bit is set with every
change of state of FRS1.TS16LFA.
Alarm Indication Signal TS 16 Status Change
The alarm indication signal AIS in timeslot 16 for the 64 kbit/s channel
associated signaling is detected or cleared. A change in bit
FRS1.TS16AIS sets this interrupt (This bit is set if the incoming TS 16
signal contains less than 4 zeros in each of two consecutive TS16-
multiframe periods.).
Remote Alarm TS 16 Status Change
A change in the remote alarm bit in CAS multiframe alignment word
is detected.
Auxiliary Pattern Indication
This bit is set if the auxiliary pattern is detected in the received bit
stream and bit FRS0.AUXP is set.
If register IPC.SCI is high this interrupt status bit is set with every
change of state of FRS0.AUXP.
Receive Slip Negative
The frequency of the receive route clock is greater than the frequency
of the receive system interface working clock based on 2.048 MHz. It
is set during alarm simulation.
In 2-frame buffer mode a frame is skipped.
Receive Slip Positive
The frequency of the receive route clock is less than the frequency of
the receive system interface working clock based on 2.048 MHz. It is
set during alarm simulation.
In 2-frame buffer mode a frame is repeated.
255
FALC-LH V1.3
E1 Registers
PEB 2255
2000-07