PEB2255H-V13 Infineon Technologies, PEB2255H-V13 Datasheet - Page 250
![IC INTERFACE LINE 80-MQFP](/photos/6/94/69416/peb2255h-v13_sml.jpg)
PEB2255H-V13
Manufacturer Part Number
PEB2255H-V13
Description
IC INTERFACE LINE 80-MQFP
Manufacturer
Infineon Technologies
Datasheet
1.PEB2255H-V13.pdf
(374 pages)
Specifications of PEB2255H-V13
Applications
*
Interface
*
Voltage - Supply
*
Package / Case
80-SQFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PEB2255H-V13
PEB2255H-V13IN
PEB2255H-V13IN
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PEB2255H-V13
Manufacturer:
Infineon Technologies
Quantity:
10 000
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RFS…
T8MS…
RMB…
CASC…
CRC4…
SA6SC…
Data Sheet
Receive Frame Start
This is an early receiver interrupt activated after the start of a valid
frame has been detected, i.e. after an address match (in operation
modes providing address recognition), or after the opening flag
(transparent mode 0) is detected, delayed by two bytes. After an RFS
interrupt, the contents of
is valid and can be read by the CPU.
Receive Time Out 8 msec
Only active if multiframing is enabled.
The
FRS0.LFA = 0 and is searching for the multiframing. This interrupt is
set to indicate that no multiframing could be found within a time
window of 8 msec. In multiframe synchronous state this interrupt is
not generated. Refer also to Floating multiframe alignment window.
Receive Multiframe Begin
This bit is set with the beginning of a received CRC multiframe related
to the internal receive line timing.
In CRC multiframe format FMR2.RFS1 = 1 or in doubleframe format
FMR2.RFS1...0 = 01 this interrupt occurs every 2 msec. If
FMR2.RFS1...0 = 00 this interrupt is generated every doubleframe
(512 bits).
Received CAS Information Changed
This bit is set with the updating of a received CAS multiframe
information in the registers RS1...16. If the last received CAS
information is different to the previous received one, this interrupt is
generated after update has been completed. This interrupt occurs
only in TS0 and TS16 synchronous state. The registers RS1...16
should be read within the next 2 ms otherwise the contents may be
lost.
Receive CRC4 Error
Receive SA6-Bit Status Changed
With every change of state of the received SA6-bit combinations this
interrupt is set.
0...
1...
• RSIS-bits 3...1
No CRC4 error occurs.
The CRC4 check of a received submultiframe failed.
framer
has
found
250
the
doubleframing
FALC-LH V1.3
(basic
E1 Registers
PEB 2255
framing)
2000-07
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