PEB2255H-V13 Infineon Technologies, PEB2255H-V13 Datasheet - Page 150

• Manufacturer Part Number: PEB2255H-V13
• Description: IC INTERFACE LINE 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2255H-V13

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2255H-V13; PEB2255H-V13IN

5.5.2
• Automatic remote alarm (Yellow Alarm) access
• Automatic AIS to system interface
• Automatic clock source switching
• Automatic freeze signaling:
5.5.3
The FALC
record code violations, framing bit errors, CRC6 bit errors, errored blocks and PRBS bit
errors. Each of the error counters is buffered. Updating the buffer is done in two modes:
• one second accumulation
• on demand via handshake with writing to the DEC register
In the one second mode an internal one second timer updates these buffers and reset
the counter to accumulate the error events in the next one second period. The error
counter can not overflow. Error events occurring during reset are not lost.
5.5.4
The FALC
alarms or error events in the received data:
framing errors, CRC errors, code violations, loss of frame alignment, loss of signal, alarm
indication signal, receive and transmit slips.
With a programmable interrupt mask register IMR4 all these alarms or error events can
generate an Errored Second Interrupt (ISR3.ES) if enabled.
5.5.5
Additionally a one second timer interrupt is generated internally to indicate that the
enabled alarm status bits or the error counters have to be checked. The timing is derived
from RCLK.
Data Sheet
If the receiver has lost its synchronization (FRS0.LFA) a remote alarm (yellow alarm)
can be sent to the distant end automatically, if enabled by bit FMR2.AXRA. In
synchronous state the remote alarm bit is removed.
In asynchronous state the synchronizer enforces an AIS to the receive system
interface automatically. However, received data may be switched through
transparently if bit FMR2.DAIS is set.
In Slave mode (LIM0.MAS = 0) the DCO-R synchronizes to the recovered route clock.
In case of Loss of Signal LOS the DCO-R switches to Master mode automatically.
Updating of the received signaling information is controlled by the freeze signaling
status. Optionally automatic freeze signaling can be disabled by setting bit SIC3.DAF.
®
®
-LH offers five error counters where each of them has a length of 16 bit. They
Auto Modes
Error Counter
Errored Second
Second Timer
-LH supports the error performance monitoring by detecting the following
150
Functional Description T1/J1
FALC-LH V1.3
PEB 2255
2000-07