PEB2255H-V13 Infineon Technologies, PEB2255H-V13 Datasheet - Page 76

• Manufacturer Part Number: PEB2255H-V13
• Description: IC INTERFACE LINE 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2255H-V13

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2255H-V13; PEB2255H-V13IN

4.3.1
Similar to the receive signaling controller the same signaling methods and the same time
slot assignment is provided. The FALC
link methods:
4.3.1.1
The transmit signaling controller of the FALC
generation, zero bit-stuffing and programmable IDLE code generation. Buffering of
transmit data is done in the 64 byte deep XFIFO. The signaling information is internally
multiplexed with the data applied to port XDI or XSIG.
In signaling controller transparent mode, fully transparent data transmission without
HDLC framing is performed. Optionally the FALC
transmission of the XFIFO contents.
The FALC
combinations of time slots may be programmed separately for the receive and transmit
directions.
4.3.1.2
The FALC
follows:
- the access via register XSW
- the access via registers XSA4E...XSA8E, capable of storing the information for a
complete multiframe
- the access via the 64 byte deep XFIFO of the signaling controller. This S
gives the opportunity to send a transparent bit stream as well as HDLC frames where the
signaling controller automatically processes the HDLC protocol. Any combination of S
bits which shall be inserted into the outgoing data stream may be selected by
XC0.SA4E...SA8E.
4.3.1.3
In external signaling mode the signaling data is received on port XSIG. The signaling
data is sampled with the working clock of the transmit system interface (SCLKX) in
conjunction with the transmit synchronization pulse (SYPX). Data on XSIG is latched in
the bit positions 5...8 per time slot, bits 1...4 are ignored. Time slot 0 and 16 are sampled
completely (bit 1...8). The received CAS multiframe is inserted frame aligned into the
data stream on XDI. Data sourced by the internal signaling controller overwrites the
external signaling data. CAS data is read from XSIG during the last frame of a
multiframe, if CRC4/multiframe mode is selected. The CAS-multiframe is aligned to the
CRC4-multiframe. Other frames are ignored.
Data Sheet
®
®
Transmit Signaling Controller (E1)
HDLC or LAPD access
S
Channel Associated Signaling CAS (E1, serial access mode)
-LH supports the S
-LH offers the flexibility to insert data during certain time slots. Any
a
bit Access (E1)
a
bit signaling of time slot 0 of every second frame as
®
-LH performs the following signaling and data
76
®
-LH performs the FLAG generation, CRC
®
-LH supports the continuous
Functional Description E1
FALC-LH V1.3
a
PEB 2255
bit access
2000-07
a