PEB2255H-V13 Infineon Technologies, PEB2255H-V13 Datasheet - Page 195

IC INTERFACE LINE 80-MQFP

PEB2255H-V13

Manufacturer Part Number
PEB2255H-V13
Description
IC INTERFACE LINE 80-MQFP
Manufacturer
Infineon Technologies
Datasheet

Specifications of PEB2255H-V13

Applications
*
Interface
*
Voltage - Supply
*
Package / Case
80-SQFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PEB2255H-V13
PEB2255H-V13IN

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PEB2255H-V13
Manufacturer:
Infineon Technologies
Quantity:
10 000
SIM…
Framer Mode Register 1 (Read/Write)
Value after RESET: 00
MFCS…
AFR…
ENSA…
Data Sheet
FMR1
MFCS
7
Alarm Simulation
0…
1…
Multiframe Force Resynchronization
Only valid if CRC multiframe format is selected (FMR2.RFS1/0=10).
A transition from low to high initiates the resynchronization procedure
for CRC-multiframe alignment without influencing doubleframe
synchronous state. In case, “Automatic Force Resynchronization”
(FMR1.AFR) is enabled and multiframe alignment can not be
regained, a new search of doubleframe (and CRC multiframe) is
automatically initiated.
Automatic Force Resynchronization
Only valid if CRC multiframe format is selected (FMR2.RFS1/0=10).
If this bit is set, a search of doubleframe alignment is automatically
initiated if two multiframe patterns with a distance of n
not been found within a time interval of 8 ms after doubleframe
alignment has been regained.
Enable S
0…
1…
Note:MFCS is not reset automatically.
AFR
H
Normal operation.
Initiates internal error simulation of AIS, loss of signal, loss of
synchronization, remote alarm, slip, framing errors, CRC
errors, and code violations. The error counters FEC, CVC,
CEC1 are incremented.
Normal operation. The S
XSW.XY0…4 and written to bits RSW.RY0…4.
S
registers XSA4...8. In addition, the received information is
written to registers RSA4...8. Transmitting of the contents of
registers XSA4...8 is disabled if one of time slot 0 transparent
modes is enabled (XSP.TT0 or TSWM.SA4...8).
a
-bit register access. The S
ENSA
a
-Bit Access via Register XSA4...8
PMOD
195
XFS
a
-bit information is taken from bits
a
-bit information is taken from the
ECM
IMOD
FALC-LH V1.3
XAIS
E1 Registers
0
PEB 2255
2 ms have
2000-07
(1B)

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