PEB2255H-V13 Infineon Technologies, PEB2255H-V13 Datasheet - Page 198

• Manufacturer Part Number: PEB2255H-V13
• Description: IC INTERFACE LINE 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2255H-V13

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2255H-V13; PEB2255H-V13IN

AXRA…
ALMF…
Data Sheet
Automatic Transmit Remote Alarm
0…
1…
Automatic Loss of Multiframe
0…
1…
ignored. With XSP.TT0=1 timeslot 0 is also looped. If
XSP.TT0=0 timeslot 0 is generated internally. AIS is sent
immediately on port RDO by setting the FMR2.SAIS bit. It is
recommended to write the actual value of XC1 into this register
once again, because a write access to register XC1 sets the
read/write pointer of the transmit elastic buffer into its optimal
position to ensure a maximum wander compensation (the write
operation forces a slip).
Normal operation
The Remote Alarm bit is set automatically in the outgoing data
stream if the receiver is in asynchronous state (FRS0.LFA bit is
set). In synchronous state the remote alarm bit is reset.
Additionally
FMR3.EXTIW =1 and the 400 ms timeout has elapsed, the
remote alarm bit is active in the outgoing data stream. In
multiframe synchronous state the outgoing remote alarm bit is
cleared.
The receiver searches a new basic framing and multiframing if
more than 914 CRC errors have been detected in a time
interval of one second. The internal 914 CRC error counter is
reset if the multiframe synchronization is found. Incrementing
the counter is only enabled in the multiframe synchronous
state.
Normal operation
in
198
multiframe
format
FMR2.RFS1=1
FALC-LH V1.3
E1 Registers
PEB 2255
2000-07
and