PEB2255H-V13 Infineon Technologies, PEB2255H-V13 Datasheet - Page 262

IC INTERFACE LINE 80-MQFP

PEB2255H-V13

Manufacturer Part Number
PEB2255H-V13
Description
IC INTERFACE LINE 80-MQFP
Manufacturer
Infineon Technologies
Datasheet

Specifications of PEB2255H-V13

Applications
*
Interface
*
Voltage - Supply
*
Package / Case
80-SQFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PEB2255H-V13
PEB2255H-V13IN

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PEB2255H-V13
Manufacturer:
Infineon Technologies
Quantity:
10 000
XRES…
XHF…
XTF…
XME…
SRES…
Data Sheet
Transmitter Reset
The transmit framer and transmit line interface excluding the pulse
shaper is reset. However the contents of the control registers is not
deleted. Transmitter reset shall be done after every new device
initialization.
Transmit HDLC Frame
After having written up to 32 bytes to the XFIFO, this command
initiates the transmission of a HDLC frame.
Transmit Transparent Frame
Initiates the transmission of a transparent frame without HDLC
framing.
Transmit Message End
Indicates that the data block written last to the transmit FIFO
completes the current frame. The FALC
transmission operation properly by appending the CRC and the
closing flag sequence to the data.
Signaling Transmitter Reset
The transmitter of the signaling controller is reset. XFIFO is cleared of
any data and an abort sequence (seven 1’s) followed by interframe
time fill is transmitted. In response to XRES an XPR interrupt is
generated. Signaling transmitter reset shall be done after every new
device initialization.
This command can also be used by the CPU to abort a frame
currently in transmission.
Note: The maximum time between writing to the CMDR register and
the execution of the command takes 2.5 periods of the current
system data rate. Therefore, if the CPU operates with a very
high clock rate in comparison with the FALC
recommended that bit SIS.CEC should be checked before
writing to the CMDR register to avoid any loss of commands.
All bits except XREP are cleared automatically.
262
®
-LH can terminate the
®
FALC-LH V1.3
T1/J1 Registers
-LH's clock, it is
PEB 2255
2000-07

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