PEB2255H-V13 Infineon Technologies, PEB2255H-V13 Datasheet - Page 129

• Manufacturer Part Number: PEB2255H-V13
• Description: IC INTERFACE LINE 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2255H-V13

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2255H-V13; PEB2255H-V13IN

Transmit Direction
FS/DL data on system transmit highway (XDI), time slot 0.
Figure 48
5.3.1
Similar to the receive signaling controller the same signaling methods and the same time
slot assignment are provided. The FALC
link methods.
5.3.1.1
The transmit signaling controller of the FALC
generation, zero bit-stuffing and programmable IDLE code generation. Buffering of
transmit data is done in the 64 byte deep XFIFO. The signaling information is multiplexed
internally with the data applied on port XDI or XSIG.
In signaling controller transparent mode, fully transparent data transmission without
HDLC framing is performed. Optionally the FALC
transmission of the XFIFO contents.
Operating in HDLC or BOM mode “flags” or “idle” may be transmitted as interframe
timefill. The FALC
combinations of time slots may be programmed separately for the receive and transmit
directions.
5.3.1.2
The signaling controller inserts the bit stream either on the transmit line side or if external
signaling is enabled on the transmit system side. Signaling data may be sourced
internally from registers XS1-12 or externally on port XSIG.
In external signaling mode the signaling data is sampled with the working clock of the
transmit system interface (SCLKX) in conjunction with the transmit synchronous pulse
(SYPX). Data on XSIG is latched in the bit positions 5-8 per time slot, bits 1-4 are
Data Sheet
Transmit Signaling Controller (T1/J1)
HDLC or LAPD access
CAS Bit-robbing (T1/J1)
Transmit FS/DL Bits on XDI (T1/J1)
®
-LH offers the flexibility to insert data during certain time slots. Any
MSB
1
2
3
FS/DL Time-Slot
®
4
-LH performs the following signaling and data
129
®
-LH performs the FLAG generation, CRC
5
6
®
-LH supports the continuous
Functional Description T1/J1
7
FS/DL
LSB
8
FS/DL Data Bit
FALC-LH V1.3
ITD06460
PEB 2255
2000-07