PEB2255H-V13 Infineon Technologies, PEB2255H-V13 Datasheet - Page 188
![IC INTERFACE LINE 80-MQFP](/photos/6/94/69416/peb2255h-v13_sml.jpg)
PEB2255H-V13
Manufacturer Part Number
PEB2255H-V13
Description
IC INTERFACE LINE 80-MQFP
Manufacturer
Infineon Technologies
Datasheet
1.PEB2255H-V13.pdf
(374 pages)
Specifications of PEB2255H-V13
Applications
*
Interface
*
Voltage - Supply
*
Package / Case
80-SQFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PEB2255H-V13
PEB2255H-V13IN
PEB2255H-V13IN
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PEB2255H-V13
Manufacturer:
Infineon Technologies
Quantity:
10 000
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CASM…
EITS…
ITF…
RFT1...0...
Data Sheet
CAS Synchronization Mode
Determines the synchronization mode of the channel associated
signaling multiframe alignment.
0…
1…
Enable Internal Time Slot 0-31 Signaling
0…
1…
Interframe Time Fill
Determines the idle (= no data to send) state of the transmit data
coming from the signaling controller.
0…
1…
RFIFO Threshold Level
The size of the accessible part of RFIFO can be determined by
programming these bits. The number of valid bytes after a RPF
interrupt is given in the following table:
RFT1
0
0
1
1
The value of RFT1, 0 can be changed dynamically.
– If reception is not running or
– after the current data block has been read, but before the
command CMDR.RMC is issued (interrupt controlled data
transfer).
Synchronization is done in accordance to ITU-T G. 732
Synchronization is established when two consecutively correct
multiframe alignment pattern are found.
Internal signaling in time slots 0-31 defined via registers
RTR1...4 or TTR1...4 is disabled.
Internal signaling in time slots 0-31 defined via registers
RTR1...4 or TTR1...4 is enabled.
Continuous logical ‘1’ is output
Continuous flag sequences are output (‘01111110’ bit patterns)
RFT0
0
1
0
1
188
Size of Accessible Part of RFIFO
32 bytes (RESET value)
16 bytes
4 bytes
2 bytes
FALC-LH V1.3
E1 Registers
PEB 2255
2000-07
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