PEB2255H-V13 Infineon Technologies, PEB2255H-V13 Datasheet - Page 268

• Manufacturer Part Number: PEB2255H-V13
• Description: IC INTERFACE LINE 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2255H-V13

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2255H-V13; PEB2255H-V13IN

Common Configuration Register 3 (Read/Write)
Value after RESET: 00
Unused bits have to be cleared.
PRE1...0…
EPT…
Note: The ’Shared Flag’ feature is not influenced by preamble transmission.
RADD…
RCRC…
Data Sheet
CCR3
Zero bit insertion is disabled during preamble transmission.
PRE1
7
Number of Preamble Repetitions
If preamble transmission is enabled, the preamble defined by register
PRE is transmitted:
00... 1 time
01... 2 times
10... 4 times
11... 8 times
Enable Preamble Transmission
This bit enables transmission of preamble. The preamble is started
after interframe timefill transmission has been stopped and a new
frame is to be transmitted. The preamble consists of an 8-bit pattern
repeated a number of times. The pattern is defined by register PRE,
the number of repetitions is selected by bits PRE0 and PRE1.
Receive Address Pushed to RFIFO
If this bit is set, the received HDLC address information (1 or 2 bytes,
depending on the address mode selected via MODE.MDS0) is
pushed to RFIFO. See
description.
Receive CRC ON/OFF
If this bit is set, the received CRC checksum is written to RFIFO
(CRC-ITU-T: 2 bytes). The checksum, consisting of the 2 last bytes in
the received frame, is followed in the RFIFO by the status information
byte (contents of register RSIS). The received CRC checksum is
additionally checked for correctness. If non-auto mode is selected,
the limits for “Valid Frame” check are modified (refer to RSIS.VFR and
to
PRE0
Chapter 8.1
H
EPT
on page 169).
RADD
268
Chapter 8.1
RCRC
on page
XCRC
169
FALC-LH V1.3
T1/J1 Registers
0
for detailed
PEB 2255
2000-07
(0A)