PEB2255H-V13 Infineon Technologies, PEB2255H-V13 Datasheet - Page 13

• Manufacturer Part Number: PEB2255H-V13
• Description: IC INTERFACE LINE 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2255H-V13

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2255H-V13; PEB2255H-V13IN

List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Figure 26
Figure 27
Figure 28
Figure 29
Figure 30
Figure 31
Figure 32
Figure 33
Figure 34
Figure 35
Figure 36
Figure 37
Figure 38
Figure 39
Figure 40
Figure 41
Figure 42
Data Sheet
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Multiple E1/T1/J1 Link over Frame Relay . . . . . . . . . . . . . . . . . . . . . . 22
8 Channel E1/T1/J1 Interface to the ATM Layer . . . . . . . . . . . . . . . . . 23
Multiple FALC Clocking Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
FIFO Word Access (Intel Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
FIFO Word Access (Motorola Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Block Diagram of Test Access Port and Boundary Scan . . . . . . . . . . . 53
Receive Clock System (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Receiver Configuration (E1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Jitter Attenuation Performance (E1). . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Jitter Tolerance (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Transmit Clock System (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
The Receive Elastic Buffer as Circularly Organized Memory . . . . . . . 65
2.048 MHz Receive Signaling Highway (E1) . . . . . . . . . . . . . . . . . . . . 68
System Interface (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Receive System Interface Clocking (E1) . . . . . . . . . . . . . . . . . . . . . . . 71
Transmit System Interface Clocking: 2.048 MHz (E1) . . . . . . . . . . . . . 74
Transmit System Interface Clocking: 8.192 MHz/4.096 Mbit/s (E1). . . 75
2.048 MHz Transmit Signaling Highway (E1) . . . . . . . . . . . . . . . . . . . 77
Transmitter Configuration (E1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Transmit Line Monitor Configuration (E1) . . . . . . . . . . . . . . . . . . . . . . 81
Data Flow in Transparent Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
CRC4 Multiframe Alignment Recovery Algorithms . . . . . . . . . . . . . . . 92
Remote Loop (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Payload Loop (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Local Loop (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Single Channel Loopback (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Receive Clock System (T1/J1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Receiver Configuration (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Jitter Attenuation Performance (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . 107
Jitter Tolerance (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Transmit Clock System (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
The Receive Elastic Buffer as Circularly Organized Memory . . . . . . 113
System Interface (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Receive System Interface Clocking (T1/J1) . . . . . . . . . . . . . . . . . . . . 119
2.048 Mbit/s Receive Signaling Highway (T1/J1) . . . . . . . . . . . . . . . 120
1.544 Mbit/s Receive Signaling Highway (T1/J1) . . . . . . . . . . . . . . . 120
Receive FS/DL Bits in Time Slot 0 on RDO (T1/J1). . . . . . . . . . . . . . 122
Transmit System Interface Clocking: 1.544 MHz (T1/J1). . . . . . . . . . 124
13
FALC-LH V1.3
PEB 2255
2000-07
Page