PEB2255H-V13 Infineon Technologies, PEB2255H-V13 Datasheet - Page 232

• Manufacturer Part Number: PEB2255H-V13
• Description: IC INTERFACE LINE 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2255H-V13

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2255H-V13; PEB2255H-V13IN

AIS…
LFA…
Data Sheet
Alarm Indication Signal
The function of this bit is determined by FMR0.ALM.
FMR0.ALM = 0:
FMR0.ALM = 1:
The bit is also set during alarm simulation and reset if FMR0.SIM is
cleared and no alarm condition exists.
With the rising edge of this bit an interrupt status bit (ISR2.AIS) is set.
Loss of Frame Alignment
This bit is set after detecting 3 or 4 consecutive incorrect FAS words
or 3 or 4 consecutive incorrect service words (can be disabled). With
the rising edge of this bit an interrupt status bit (ISR2.LFA) is set. The
specification of the loss of sync conditions is done via bits RC1.SWD
and RC1.ASY4. After loss of synchronization, the frame aligner
resynchronizes automatically.
The following conditions have to be detected to regain synchronous
state:
– The presence of the correct FAS word in frame n.
– The presence of the correct service word (bit 2 = 1) in frame n + 1.
– For a second time the presence of a correct FAS word in frame
The bit is cleared when synchronization has been regained (directly
after the second correct FAS word of the procedure described above
has been received).
If the CRC-multiframe structure is enabled by setting bit FMR2.RFS1,
multiframe alignment is assumed to be lost if pulse-frame
synchronization has been lost. The resynchronization procedure for
multiframe alignment starts after the bit FRS0.LFA has been cleared.
n + 2.
This bit is set when two or less zeros in the
received bit stream are detected in a time interval
of 250 s and the FALC
state (FRS0.LFA = 1). The bit is reset when no
alarm condition is detected (according to ETSI
standard).
This bit is set when the incoming signal has two or
less Zeros in each of two consecutive double
frame period (512 bits). This bit is cleared when
each of two consecutive doubleframe periods
contain three or more zeros or when the frame
alignment signal FAS has been found. (according
to ITU-T G.775 standard)
232
®
-LH is in asynchronous
FALC-LH V1.3
E1 Registers
PEB 2255
2000-07