PEB2255H-V13 Infineon Technologies, PEB2255H-V13 Datasheet - Page 63

• Manufacturer Part Number: PEB2255H-V13
• Description: IC INTERFACE LINE 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2255H-V13

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2255H-V13; PEB2255H-V13IN

• Generation of control signals to synchronize the CRC checker and the receive elastic
If programmed and applicable to the selected multiframe format, CRC checking of the
incoming data stream is done by generating check bits for a CRC submultiframe
according to the CRC 4 procedure (refer to ITU-T G704). These bits are compared with
those check bits that are received during the next CRC submultiframe. If there is at least
one mismatch, the CRC error counter (16 bit) is incremented.
4.1.11
The received bit stream is stored in the receive elastic buffer. The memory is organized
as a two-frame elastic buffer with a maximum size of 64
buffer can be configured independently for the receive and transmit direction.
Programming of the receive buffer size is done by SIC1.RBS1/0 :
• RBS1/0 = 00 : two frame buffer or 512 bits
• RBS1/0 = 01 : one frame buffer or 256 bits
• RBS1/0 = 10 : short buffer or 92 bits :
• RBS1/0 = 11 : Bypass of the receive elastic buffer, (SYPR = output)
The functions are:
• Clock adaption between system clock (SCLKR) and internally generated route clock
• Compensation of input wander and jitter.
• Frame alignment between system frame and receive route frame
• Reporting and controlling of slips
Controlled by special signals generated by the receiver, the unipolar bit stream is
converted into bit-parallel data which is circularly written to the elastic buffer using
internally generated Receive Route Clock (RCLK).
Reading of stored data is controlled by the System Clock sourced by SCLKR and the
Synchronous Pulse (SYPR) in conjunction with the programmed offset values for the
receive time slot/clock slot counters. After conversion into a serial data stream, the data
Data Sheet
buffer.
Maximum of wander amplitude (peak-to-peak): 190 UI (1 UI = 488 ns )
average delay after performing a slip: about 1 frame
Max. wander amplitude: 94 UI
average delay after performing a slip: 128 bits, (SYPR = output)
Max. wander amplitude: 18 µs
average delay after performing a slip: 46 bits, (SYPR = output)
(RCLK).
Receive Elastic Buffer (E1)
63
Functional Description E1
8 bit. The size of the elastic
FALC-LH V1.3
PEB 2255
2000-07