PEB2255H-V13 Infineon Technologies, PEB2255H-V13 Datasheet - Page 184

• Manufacturer Part Number: PEB2255H-V13
• Description: IC INTERFACE LINE 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2255H-V13

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2255H-V13; PEB2255H-V13IN

XRES…
XHF…
XTF…
XME…
SRES…
Data Sheet
Transmitter Reset
The transmit framer and transmit line interface including DCO-X are
reset. However, the contents of the control registers is not deleted.
XRES has to be given every time after a configuration change.
Transmit HDLC Frame
After having written up to 32 bytes to the XFIFO, this command
initiates the transmission of a HDLC frame.
Transmit Transparent Frame
Initiates the transmission of a transparent frame without HDLC
framing.
Transmit Message End
Indicates that the data block written last to the transmit FIFO
completes the current frame. The FALC
transmission operation properly by appending the CRC and the
closing flag sequence to the data.
Signaling Transmitter Reset
The transmitter of the signaling controller is reset. XFIFO is cleared of
any data and an abort sequence (seven 1's) followed by interframe
time fill is transmitted. In response to SRES a XPR interrupt is
generated.
This command can be used by the CPU to abort a frame currently in
transmission.
Note: The maximum time between writing to the CMDR register and
Note: Bits are cleared automatically except of XREP
the execution of the command takes 2.5 periods of the current
system data rate. Therefore, if the CPU operates with a very
high clock rate in comparison with the FALC
recommended that bit SIS.CEC should be checked before
writing to the CMDR register to avoid any loss of commands.
184
®
-LH can terminate the
®
FALC-LH V1.3
-LH's clock, it is
E1 Registers
PEB 2255
2000-07