PEB2255H-V13 Infineon Technologies, PEB2255H-V13 Datasheet - Page 242

IC INTERFACE LINE 80-MQFP

PEB2255H-V13

Manufacturer Part Number
PEB2255H-V13
Description
IC INTERFACE LINE 80-MQFP
Manufacturer
Infineon Technologies
Datasheet

Specifications of PEB2255H-V13

Applications
*
Interface
*
Voltage - Supply
*
Package / Case
80-SQFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PEB2255H-V13
PEB2255H-V13IN

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PEB2255H-V13
Manufacturer:
Infineon Technologies
Quantity:
10 000
CRC Error Counter 2 (Read)
CC15…0…
Data Sheet
CEC2H
CEC2L
CC15
CC7
7
7
CRC Error Counter (Reported from TE via Sa6 -Bit)
Depending on bit LCR1.EPRM the error counter increment is
selected:
LCR1.EPRM=0:
If doubleframe format is selected, CEC2H/L has no function. If CRC-
multiframe mode is enabled, CEC2H/L works as SA6 Bit error
indication counter (16 bits) which counts the SA6 Bit sequence 0001
and 0011in every received CRC submultiframe.
Incrementing the counter is only possible in the multiframe
synchronous state FRS0.LMFA = 0.
SA6 Bit sequence: SA61, SA62, SA63, SA64 = 0001 or 0011 where
SA61 is received in frame 1 or 9 in every multiframe.
Pseudo Random Bit Sequence Error Counter
LCR1.EPRM=1:
This 16-bit counter is incremented with every received PRBS bit error
in the PRBS synchronous state RSP.LLBAD = 1. The error counter
doesn’t roll over.
During alarm simulation, the counter is incremented once per
submultiframe up to its saturation.
Clearing and updating the counter is done according to bit
FMR1.ECM.
If this bit is reset the error counter is permanently updated in the
buffer. For correct read access of the error counter bit DEC.DCEC2
has to be set. With the rising edge of this bit updating the buffer is
stopped and the error counter is reset. Bit DEC.DCEC2 is reset
automatically with reading the error counter high byte.
If FMR1.ECM is set every second (interrupt ISR3.SEC) the error
counter is latched and then automatically reset. The latched error
counter state should be read within the next second.
242
FALC-LH V1.3
CC0
CC8
E1 Registers
0
0
PEB 2255
2000-07
(58)
(59)

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