PEB2255H-V13 Infineon Technologies, PEB2255H-V13 Datasheet - Page 169

• Manufacturer Part Number: PEB2255H-V13
• Description: IC INTERFACE LINE 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2255H-V13

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2255H-V13; PEB2255H-V13IN

8
The HDLC controller can be programmed to operate in various modes, which are
different in the treatment of the HDLC frame in receive direction. Thus, the receive data
flow and the address recognition features can be performed in a very flexible way, to
satisfy almost any practical requirements.
There are 4 different operating modes which can be set via the MODE register.
8.1
All frames with valid addresses are forwarded directly via the RFIFO to the system
memory.
Depending on the selected address mode, the FALC
address recognition (MODE.MDS0).
If a 2-byte address field is selected, the high address byte is compared with the fixed
value FEH or FCH (group address) as well as with two individually programmable values
in RAH1 and RAH2 registers. According to the ISDN LAPD protocol, bit 1 of the high byte
address is interpreted as command/response bit (C/R) and is excluded from the address
comparison to RAH1.
Similarly, two compare values can be programmed in special registers (RAL1, RAL2) for
the low address byte. A valid address is recognized in case the high and low byte of the
address field correspond to one of the compare values. Thus, the FALC
called (addressed) with 6 different address combinations. HDLC frames with address
fields that do not match any of the address combinations, are ignored by the FALC
In case of a 1-byte address, RAL1 and RAL2 are used as compare registers. The HDLC
control field, data in the I-field and an additional status byte are temporarily stored in the
RFIFO. Additional information can also be read from a special register (RSIS).
As defined by the HDLC protocol, the FALC
(bit-stuffing) in the transmit/receive data stream automatically. That means, it is
guaranteed that at least a “0” will appear after 5 consecutive “1”s.
8.1.1
Characteristics: address recognition, FLAG - and CRC generation/check, bit-stuffing
All frames with valid addresses are forwarded directly via the RFIFO to the system
memory.
8.1.2
Characteristics: address recognition, FLAG - and CRC generation/check, bit-stuffing
Only the high byte of a 2-byte address field is compared with registers RAH1/2. The
whole frame excluding the first address byte is stored in RFIFO.
Data Sheet
Signaling Controller Operating Modes
HDLC Mode
Non-Auto-Mode (MODE.MDS2...1 = 01)
Transparent Mode 1 (MODE.MDS2...0 = 101)
169
®
-LH performs the zero bit insertion/deletion
Signaling Controller Operating Modes
®
-LH can perform a 1 or 2 byte
FALC-LH V1.3
®
PEB 2255
-LH can be
2000-07
®
-LH.