PEB2255H-V13 Infineon Technologies, PEB2255H-V13 Datasheet - Page 234

IC INTERFACE LINE 80-MQFP

PEB2255H-V13

Manufacturer Part Number
PEB2255H-V13
Description
IC INTERFACE LINE 80-MQFP
Manufacturer
Infineon Technologies
Datasheet

Specifications of PEB2255H-V13

Applications
*
Interface
*
Voltage - Supply
*
Package / Case
80-SQFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PEB2255H-V13
PEB2255H-V13IN

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PEB2255H-V13
Manufacturer:
Infineon Technologies
Quantity:
10 000
LMFA…
Framer Receive Status Register 1 (Read)
TS16RA…
TS16LOS…
TS16AIS…
Data Sheet
FRS1
7
TS16RA
Loss of Multiframe Alignment
Not used in doubleframe format (FMR2.RFS1 = 0). In this case, LMFA
is set.
In CRC-multiframe mode (FMR2.RFS1 = 1), this bit is set
– if force resynchronization is initiated by setting bit FMR0.FRS, or
– if multiframe force resynchronization is initiated by setting bit
– if pulseframe alignment has been lost (FRS0.LFA).
It is reset if two CRC-multiframes have been received at an interval of
n
If bit FRS0.LMFA is cleared a loss of multiframe alignment recovery
interrupt status ISR2.MFAR is generated.
Receive Timeslot 16 Remote Alarm
This bit contains the actual information of the received remote alarm
bit RS1.2 in time slot 16. Setting and resetting of this bit causes an
interrupt status change ISR3.RA16.
Receive Timeslot 16 Loss of Signal
This bit is set if the incoming TS16 data stream contains always zeros
for at least 16 contiguously received time slots. A one in a time slot 16
resets this bit.
Receive Timeslot 16 Alarm Indication Signal
The detection of the alarm indication signal in timeslot 16 is according
to ITU-T G.775.
This bit is set if the incoming TS16 contains less than 4 zeros in each
of two consecutive TS16 multiframe periods. This bit is cleared if two
consecutive received CAS multiframe periods contains more than 3
zeros or the multiframe pattern was found in each of them. This bit is
cleared if TS0 synchronization is lost.
FMR1.MFCS, or
2 ms (n = 1, 2, 3…) without a framing error.
TS16LOS
TS16AIS TS16LFA
234
XLS
FALC-LH V1.3
XLO
E1 Registers
0
PEB 2255
2000-07
(4D)

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