PEB2255H-V13 Infineon Technologies, PEB2255H-V13 Datasheet - Page 95

• Manufacturer Part Number: PEB2255H-V13
• Description: IC INTERFACE LINE 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2255H-V13

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2255H-V13; PEB2255H-V13IN

• Automatic clock source switching
• Automatic freeze signaling:
4.5.3
The FALC
code violations, framing bit errors, E-bit errors, CRC4 bit errors and CRC4 error events
which are flagged in the different SA6 bit combinations. Each of the error counter is
buffered. Updating the buffer is done in two modes:
• one second accumulation
• on demand via handshake with writing to the DEC register
In the one second mode an internal one second timer updates these buffers and reset
the counter to accumulate the error events in the next one second period. The error
counter can not overflow. Error events occurring during reset are not lost.
4.5.4
The FALC
alarms or error events in the received data:
framing errors, CRC errors, code violations, loss of frame alignment, loss of signal, alarm
indication signal, E bit error, receive and transmit slips.
With a programmable interrupt mask register IMR4 all these alarms or error events can
generate an Errored Second Interrupt (ISR3.ES) if enabled.
4.5.5
Additionally a one second timer interrupt is generated internally to indicate that the
enabled alarm status bits or the error counters have to be checked. The clock is derived
from signal RCLK.
4.5.6
The FALC
and down/deactivate pattern with bit error rates up to1/100. Framed or unframed in-band
loop code is selected by LCR1.FLLB. Replacing transmit data with the in-band loop
codes is done by FMR3.XLD/XLU.
The FALC
and down pattern (if LCR1.LLBP = 1) or a default pattern 00001 for up and 001 for down
(if LCR1.LLBP = 0).
Data Sheet
In Slave mode (LIM0.MAS = 0) the DCO-R synchronizes to the recovered route clock.
In case of Loss of Signal LOS the DCO-R switches automatically to Master mode.
Updating of the received signaling information is controlled by the freeze signaling
status. Optionally automatic freeze signaling can be disabled by setting bit SIC3.DAF.
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-LH offers six error counters each of them has a length of 16 bit. They record
Error Counter
Errored Second
Second Timer
In-Band Loop Generation and Detection
-LH also offers the ability to generate and detect a flexible in-band loop up
-LH generates and detects a framed or unframed in-band loop up/activate
-LH supports the error performance monitoring by detecting the following
95
Functional Description E1
FALC-LH V1.3
PEB 2255
2000-07