PEB2255H-V13 Infineon Technologies, PEB2255H-V13 Datasheet - Page 89

• Manufacturer Part Number: PEB2255H-V13
• Description: IC INTERFACE LINE 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2255H-V13

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2255H-V13; PEB2255H-V13IN

PEB 2255
FALC-LH V1.3
Functional Description E1
synchronization could not be achieved within 8 ms and is started just after the previous
frame alignment signal. The research of the basic frame alignment is done in parallel and
is independent of the synchronization procedure of the primary basic frame alignment
signal. During the parallel search all receiver functions are based on the primary frame
alignment signal, like framing errors, S
-, S
-, A-bits …). All subsequent multiframe
a
i
searches are associated with each basic framing sequence found during the parallel
search.
If the CRC4 multiframe alignment sequence was not found within the time interval of
400 ms, the receiver is switched into a non-CRC4 mode indicated by setting the bit
FRS0.NMF (No Multiframing Found) and ISR2.T400MS. In this mode checking of CRC
bits is disabled and the received E-bits are forced to low. The transmitter framing format
is not changed. Even if multiple basic FAS resynchronizations have been established
during the parallel search, the receiver is maintained to the initially determined primary
frame alignment signal location.
However, if the CRC4 multiframe alignment could be achieved within the 400 ms time
interval assuming a CRC4 to CRC4 interworking, then the basic frame alignment
sequence associated to the CRC4 multiframe alignment signal is chosen. If necessary,
the primary frame alignment signal location is adjusted according to the multiframe
alignment signal. The CRC4 performance monitoring is started if enabled by
FMR2.ALMF and the received E-bits are processed in accordance with ITU-T G.704.
Switching into the doubleframe format (non CRC4) mode after 400 ms can be disabled
®
by setting of FMR3.EXTIW. In this mode the FALC
-LH continues search for
multiframing. In the interworking mode setting of bit FMR1.AFR is not allowed.
4.4.3.6
A-Bit Access (E1)
®
If the FALC
-LH detects a remote alarm indication (bit 2 in TS0 not containing the FAS
word) in the received data stream the interrupt status bit ISR2.RA is set. With the
deactivation of the remote alarm the interrupt status bit ISR2.RAR is generated.
®
By setting FMR2.AXRA the FALC
-LH automatically transmits the remote alarm bit = 1
in the outgoing data stream if the receiver detects a loss of frame alignment
(FRS0.LFA = 1). If the receiver is in synchronous state (FRS0.LFA = 0) the remote alarm
bit is reset in the outgoing data stream.
Additionally, if bit FMR3.EXTIW is set and the multiframe synchronous state could not
be achieved within the 400 ms after finding the primary basic framing, the A-bit is
transmitted active high to the remote end until the multiframing is found.
Note: The A-bit may be processed via the system interface. Setting bit TSWM.TRA
enables transparency for the A bit in transmit direction (refer to
Table
20).
Data Sheet
89
2000-07