PEB2255H-V13 Infineon Technologies, PEB2255H-V13 Datasheet - Page 218
PEB2255H-V13
Manufacturer Part Number
PEB2255H-V13
Description
IC INTERFACE LINE 80-MQFP
Manufacturer
Infineon Technologies
Datasheet
1.PEB2255H-V13.pdf
(374 pages)
Specifications of PEB2255H-V13
Applications
*
Interface
*
Voltage - Supply
*
Package / Case
80-SQFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PEB2255H-V13
PEB2255H-V13IN
PEB2255H-V13IN
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PEB2255H-V13
Manufacturer:
Infineon Technologies
Quantity:
10 000
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LOS2...1…
Loop Code Register 1 (Read/Write)
Value after RESET: 00
EPRM…
XPRBS…
Data Sheet
LCR1
EPRM
7
XPRBS
Loss of Signal Recovery Condition
00… The LOS alarm is cleared if the predefined pulse density
01… Additionally to the recovery condition described above a LOS
10… Clearing a LOS alarm is done if the pulse density is fulfilled and
11… Not assigned.
Enable Pseudo Random Bit Sequence Monitor
0…
1…
Transmit Pseudo Random Bit Sequence
A one in this bit position enables transmitting of a pseudo random bit
sequence to the remote end. Depending on pit LLBP the PRBS is
generated according to 2
restriction ( ITU-T O. 151).
H
(register PCR) is detected during the time interval which is
defined by register PCD.
alarm is only cleared if the pulse density is fulfilled and no more
than 15 contiguous zeros are detected during the recovery
interval. (according to TR-NWT 499).
no more than 99 contiguous zeros are detected during the
recovery interval. (according to TR-NWT 820).
Pseudo random bit sequence (PRBS) monitor is disabled.
PRBS monitor is enabled. Setting this bit enables incrementing
the CEC2 error counter with each detected PRBS bit error. With
any change of state of the PRBS internal synchronization
status an interrupt ISR1.LLBSC is generated. The current
status of the PRBS synchronizer is indicated by bit
RSP.LLBAD. The expected PRBS sequence has to be selected
by bit LCR1.LLBP.
The PRBS status signal is output on pin RFSP, if
FMR3.CFRZ=0 and LCR1.EPRM=1. It is set high, if the PRBS
monitor is in synchronous state.
LDC1
LDC0
218
LAC1
15
-1 or 2
LAC0
20
-1 with a maximum-14-zero
FLLB
FALC-LH V1.3
LLBP
E1 Registers
0
PEB 2255
2000-07
(39)
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