r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1002

Manufacturer Part Number

r5s77631ay266bgv

Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series

Manufacturer

Renesas Electronics Corporation.

Section 23 Gigabit Ethernet Controller (GETHER)

The GETHER consists of the following three function units:

• DMA transfer controller (E-DMAC):

• MAC controller (E-MAC):

• Transfer Switching Unit (TSU): Transfer processing between port 0 and port 1, and CAM

Using its direct memory access (DMA) function, the E-DMAC performs DMA transfer of frame

data between a user-specified Ethernet frame transmission/reception data storage destination

(accessible memory space: transmit buffer/receive buffer) and the transmit/receive FIFO in the E-

DMAC. The user cannot read and write data from and to the transmit/receive FIFO directly via the

To enable the E-DMAC to perform DMA transfer, information (data) including a transmit/receive

data storage address and so forth, referred to as a descriptor, is required. The E-DMAC reads

transmit data from the transmit buffer or writes receive data to the receive buffer according to the

descriptor information. By arranging multiple descriptors as a descriptor row (list) (to be placed in

a readable/writable memory space), multiple Ethernet frames can be transmitted or received

continuously.

The E-DMAC consists of two systems: one for port 0 and the other for port 1, and both operate

independently for transmission and reception.

The E-MAC constructs an Ethernet frame using the data written to the transmit FIFO and

transmits the frame to the GMII/MII/RMII. It also performs a CRC check of an Ethernet frame

received from the GMII/MII/RMII and deconstructs the frame to write to the receive FIFO. The E-

MAC supports three formats MII, GMII and RMII for interface to the PHI-LSI connected

externally to this LSI.

The E-MAC consists of two controllers: E-MAC0 for port 0 and E-MAC1 for port 1, which

correspond to E-DMAC0 and E-DMAC1 respectively.

The TSU performs Ethernet frame data transfer between the E-MAC0 and E-MAC1. The TSU,

which is placed between the E-DMAC and E-MAC, references the CAM entry table to select one

of the following tasks according to the Ethernet frame destination address (DA) input to the E-

Rev. 1.00 Oct. 01, 2007 Page 936 of 1956

REJ09B0256-0100

the memory and the transmit/receive FIFO

transmit/receive FIFO and the GMII/MII/RMII

Transmission/reception processing between the

DMA transfer between the transmit/receive buffer in