r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 930

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 23 Gigabit Ethernet Controller (GETHER)
23.3.43 Relay Status Interrupt Mask Register (TSU_FWINMK)
TSU_FWINMK is a 32-bit readable/writable register that sets the interrupt mask for status bits in
TSU_FWSR.
Rev. 1.00 Oct. 01, 2007 Page 864 of 1956
REJ09B0256-0100
Bit
31 to 24
23
22
21
20
19
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
Bit Name

OVFM0
RBSYM0
RINTM60
RINTM50
RINTM40
31
15


R
R
0
0
30
14


R
R
0
0
29
13


R
R
0
0
Initial
Value
All 0
0
0
0
0
0
28
12


R
R
0
0
27
11


R
R
0
0
R/W
R
R/W
R/W
R/W
R/W
R/W
26
10

R

R
0
0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Port 0-to-1 Relay FIFO Overflow Detect Interrupt Mask
0: Interrupts disabled
1: Interrupts enabled
E-MAC-0 Overflow Alert Signal Output Interrupt Mask
0: Interrupts disabled
1: Interrupts enabled
E-MAC-0 Carrier Extension Loss Error Detect Interrupt
Mask
0: Interrupts disabled
1: Interrupts enabled
E-MAC-0 Residual-Bit Frame Receive Interrupt Mask
0: Interrupts disabled
1: Interrupts enabled
E-MAC-0 Too-Long Frame Receive Interrupt Mask
0: Interrupts disabled
1: Interrupts enabled
25


R
R
0
9
0
24


R
R
0
8
0
OVFM
OVFM
R/W
R/W
23
0
7
0
0
1
RBSYM
RBSYM
R/W
R/W
22
0
0
6
0
1
RINTM
RINTM
R/W
R/W
21
60
61
0
5
0
RINTM
RINTM
R/W
R/W
20
50
51
0
4
0
RINTM
RINTM
R/W
R/W
19
40
41
0
3
0
RINTM
RINTM
R/W
R/W
18
30
31
0
2
0
RINTM
RINTM
R/W
17
20
21
0
1
0
RINTM
RINTM
R/W
R/W
16
10
11
0
0
0