r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1027

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

(2)
(a)
If a transmission error is detected during frame transmission from the transmit FIFO to the
GMII/MII/RMII, transmission of the frame data is aborted. At this time, if DMA transfer of the
appropriate frame from the transmit buffer to the transmit FIFO has not been completed, the DMA
transfer is also aborted.
Following a write-back operation to the transmit descriptor related to the transmit frame aborted
by a transmission error, 1 is written to the TABT bit in EESR and an interrupt is issued to the
CPU. The subsequent transmit descriptors will be processed normally.
(b) Transmit FIFO Underflow
If the transmit FIFO is empty (transmit FIFO underflow) during frame transmission from the
transmit FIFO to the GMII/MII/RMII, the E-MAC forcibly aborts transmission of the frame to the
GMII/MII/RMII. At this time, the frame that the E-MAC receives from the E-DMAC is cut off
halfway. Then, the E-MAC performs the following operation:
• Writes the TFUF bit in EESR to 1 and generates an interrupt to the CPU.
• Performs a write-back operation to the transmit descriptor corresponding to the transmit frame.
• Following the write-back operation, writes the TUC bit in EESR and generates an interrupt to
The subsequent transmit descriptors operate normally.
The E-MAC waits to start frame transmission from the transmit FIFO to the GMII/MII/RMII until
the data that was stored in the transmit FIFO exceeds the number of the bytes specified by TFTR.
Through the effective use of TFTR, the transmit FIFO underflow counts can be controlled.
(c)
When the TFP bits of the descriptor previously processed are set to 00 or 10 and the TACT bit of
the read transmit descriptor is set to 0 (invalid), a transmit descriptor empty state is determined
and 1 is written to the TDE bit in EESR, and then an interrupt is issued to the CPU.
When a transmit descriptor state is empty, start transmission processing after a software reset.
the CPU.
Transmission Error Processing
Transmission Abort
Transmit Descriptor Empty
Section 23 Gigabit Ethernet Controller (GETHER)
Rev. 1.00 Oct. 01, 2007 Page 961 of 1956
REJ09B0256-0100