r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 561

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Bit
7
6
5
Bit Name
APEDI
SEDI
DPEITW
Initial
Value
0
0
0
R/W
SH: R/WC
PCI: R
SH: R/WC
PCI: R
SH: R/WC
PCI: R
Description
Address Parity Error Detection Interrupt
Indicates an address parity error has been detected.
When both the PER and SERRE bits in the PCI
command register are set to 1, an address parity
error is detected.
0: Address parity error detection interrupt does not
[Clear condition]
Write 1 to this bit (write clear).
1: Address parity error detection interrupt occurs
[Set condition]
When an address parity error detection interrupt
occurs.
SERR Detection Interrupt
Indicates that the assertion of the SERR signal has
been detected when the PCIC operates in host bus
bridge mode.
0: SERR detection interrupt does not occur
[Clear condition]
Write 1 to this bit (write clear).
1: SERR detection interrupt occurs
[Set condition]
When a SERR detection interrupt occurs.
Data Parity Error Interrupt for Target Write
Indicates that a data parity error has been detected
during a target write access (only detected when
PCICMD.PER is set to 1) when the PCIC functions
as a target.
0: Data parity error detection interrupt does not occur
[Clear condition]
Write 1 to this bit (write clear).
1: Data parity error detection interrupt occurs
[Set condition]
When a data parity error detection interrupt occurs.
occur
Rev. 1.00 Oct. 01, 2007 Page 495 of 1956
Section 13 PCI Controller (PCIC)
REJ09B0256-0100