r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1005

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 23 Gigabit Ethernet Controller (GETHER)
23.4.1
Descriptors and Descriptor List
The E-DMAC performs DMA transfer according to the information (data), referred to as a
descriptor, written in memory space. There are two types of descriptors: transmit descriptors and
receive descriptors. Before a DMA transfer, DMA transfer information including a
transmit/receive frame data storage address must be set by software.
The E-DMAC automatically starts reading a transmit/receive descriptor when the TR bits in
EDTRR are set to 11 or the RR bit in EDRRR is set to 1, and performs DMA transfer of frame
data between the transmit/receive buffer and transmit/receive FIFO according to the information
stored in the descriptor. After completion of Ethernet frame transmission/reception, the E-DMAC
disables the descriptor valid/invalid bit and reflects the result of transmission/reception in the
status bits.
Descriptors are placed in a readable/writable memory space. The address of the start descriptor
(descriptor to be read first by the E-DMAC) is set in TDLAR/RDLAR. When multiple descriptors
are prepared as a descriptor row (descriptor list), the descriptors are placed in continuous
addresses (memory) according to the descriptor length set in the DL0 and DL1 bits in EDMR.
The E-DMAC consists of two systems: one for port 0 and the other for port 1. The DMAC for
transmission and the DMAC for reception operate independently, and the DMAC for port 0 and
the DMAC for port 1 operate independently. Place descriptors for transmission and reception and
descriptors for port 0 and port 1 in those address spaces that do not overlap. If addresses are
overlapped, E-DMAC does not successfully operate.
(1)
Transmit Descriptor
Figure 23.3 shows the configuration of a transmit descriptor and the relationship with a transmit
buffer.
The data of a transmit descriptor consists of TD0, TD1, TD2, and padding data in groups of 32
bits from top to end. The length of padding data is determined according to the descriptor length
specified by the DL0 and DL1 bits in EDMR.
TD0 indicates whether the transmit descriptor is valid or invalid, and information about the
descriptor configuration and status. TD1 indicates the length of data in a transmit buffer to be
transferred (TDL) as specified by the descriptor. TD2 indicates the start address of a transmit
buffer that holds data to be transferred (TBA).
Depending on the descriptor specification, one transmit descriptor can specify all transmit data of
one frame (single-frame/single-buffer) or multiple descriptors can specify the transmit data of one
Rev. 1.00 Oct. 01, 2007 Page 939 of 1956
REJ09B0256-0100