r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1845

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

41.2.8
CCMFR is a readable/writable 32-bit register which indicates whether or not the match conditions
have been satisfied for each channel. When a channel match condition has been satisfied, the
corresponding flag bit is set to 1. To clear the flags, write the data containing value 0 for the bits
to be cleared and value 1 for the other bits to this register. (The logical AND between the value
which has been written and the current register value is actually written to the register.)
Sequential operation using multiple channels is available by using these match flags.
Bit
31 to 2
1
0
Initial value :
Initial value :
R/W:
R/W:
Bit :
Bit :
Channel Match Flag Register (CCMFR)
Bit Name
—
MF1
MF0
31
15
R
R
0
0
30
14
R
R
0
0
Initial
Value
All 0
0
0
29
13
R
R
0
0
28
12
R
R
0
0
27
11
R
R
0
0
R/W
R
R/W
R/W
26
10
R
R
0
0
Description
Reserved
For read/write in this bit, refer to General Precautions
on Handling of Product.
Channel 1 Condition Match Flag
This flag is set to 1 when the channel 1 match
condition has been satisfied. To clear the flag, write 0
to this bit.
0: Channel 1 match condition has not been satisfied.
1: Channel 1 match condition has been satisfied.
Channel 0 Condition Match Flag
This flag is set to 1 when the channel 0 match
condition has been satisfied. To clear the flag, write
0 to this bit.
0: Channel 0 match condition has not been satisfied.
1: Channel 0 match condition has been satisfied.
25
R
R
0
9
0
24
R
R
0
8
0
23
R
R
0
7
0
Rev. 1.00 Oct. 01, 2007 Page 1779 of 1956
22
R
R
0
6
0
Section 41 User Break Controller (UBC)
21
R
R
0
5
0
20
R
R
0
4
0
19
R
R
0
3
0
REJ09B0256-0100
18
R
R
0
2
0
MF1
R/W
17
R
0
1
0
MF0
R/W
16
R
0
0
0