r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 108

Manufacturer Part Number

r5s77631ay266bgv

Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series

Manufacturer

Renesas Electronics Corporation.

Section 2 Programming Model

Figure 2.3 shows the relationship between the processing modes and general registers. This LSI

has twenty-four 32-bit general registers (R0_BANK0 to R7_BANK0, R0_BANK1 to

R7_BANK1, and R8 to R15). However, only 16 of these can be accessed as general registers R0

to R15 in one processing mode. This LSI has two processing modes, user mode and privileged

• R0_BANK0 to R7_BANK0

• R0_BANK1 to R7_BANK1

Rev. 1.00 Oct. 01, 2007 Page 42 of 1956

REJ09B0256-0100

Allocated to R0 to R7 in user mode (SR.MD = 0)

Allocated to R0 to R7 when SR.RB = 0 in privileged mode (SR.MD = 1).

Cannot be accessed in user mode.

Allocated to R0 to R7 when SR.RB = 1 in privileged mode.

General Registers

SR.MD = 0 or

(SR.MD = 1, SR.RB = 0)

Figure 2.3 General Registers

(SR.MD = 1, SR.RB = 1)