r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 553

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Bit
8
7
6
5, 4
3
2
Bit Name
TBS

BMAM


IOCS
Initial
Value
0
0
0
Undefined
0
0
R/W
SH: R/W
PCI: R
SH: R
PCI: R
SH: R/W
PCI: R
SH: R
PCI: R
SH: R
PCI: R
SH: R/W
PCI: R
Description
Byte Swap
Specifies whether or not byte data is swapped when
accessing to the PCI local bus.
0: No swap
1: Byte data is swapped
Reserved
This bit is always read as 0. The write value should
always be 0.
Bus Master Arbitration
Controls the PCI bus arbitration mode when the PCIC
operates in host bus bridge mode. This bit is ignored
when the PCIC operates in normal mode.
0: Fixed mode (PCIC > device0 > device1 > device2 >
1: Pseudo round robin (the most recently granted
Reserved
These bits are always read as an undefined value.
The write value should always be 0.
Reserved
This bit is always read as 0. The write value should
always be 0.
INTA Output
Controls the INTA output by software. This bit is valid
only in normal mode.
0: Makes INTA output high-impedance state (driven
1: Asserts INTA output (low level output)
device is assigned the lowest priority)
For details, see section 13.4.3 (5), Endian or
device3)
high by pull-up register)
section 13.4.4 (6), Endian.
Rev. 1.00 Oct. 01, 2007 Page 487 of 1956
Section 13 PCI Controller (PCIC)
REJ09B0256-0100