r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 343

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

9.3.19
INT2MSKR1 is a 32-bit readable/writable register that sets masking for each source indicated in
the interrupt source register. Interrupts whose corresponding bits in INT2MSKR1 are set to 1 are
not notified to the CPU.
INT2MSK1 is initialized to H'FFFF FFFF (mask state) by a reset.
Initial value:
Initial value:
Bit
13
12
11 to 9
8
7
6
5
4
3
2
1
0
R/W:
R/W:
Bit:
Bit:
Interrupt Mask Register 1 (INT2MSKR1)
Bit Name
HAC
CMT
—
DMAC
H-UDI
—
WDT
SCIF1
SCIF0
RTC
TMU1
TMU0
PCC
Note: * This bit is reserved in the R5S77631.
R/W
31
15
−
R
1
1
30
−
14
−
R
R
1
1
Initial
Value
1
1
All 1
1
1
1
1
1
1
1
1
1
29
13
−
−
R
R
1
1
ADC
R/W
28
12
−
R
1
1
R/W
TPU
R/W
R/W
R/W
R
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
27
11
−
R
1
1
R/W
SIM SIOF2 SIOF1 LCDC
26
10
−
R
1
1
Function
Masks HAC interrupts
Masks CMT interrupts
These bits are always read as 1.
The write value should always be
1.
Masks DMAC interrupts
Masks H-UDI interrupts
This bit is always read as 1. The
write value should always be 1.
Masks WDT interrupts
Masks SCIF1 interrupts
Masks SCIF0 interrupts
Masks RTC interrupts
Masks TMU1 interrupts
Masks TMU0 interrupts
SCIF2 USBF
R/W
R/W
25
1
9
1
R/W
R/W
24
1
8
1
R/W
23
−
R
1
7
1
Rev. 1.00 Oct. 01, 2007 Page 277 of 1956
22
−
−
R
R
1
6
1
Section 9 Interrupt Controller (INTC)
STIF1 STIF0
R/W
IIC1
R/W
21
1
5
1
R/W
R/W
IIC0 SSI3 SSI2
20
1
4
1
Description
Masks interrupts for
each peripheral
module.
[When writing]
0: Invalid
1: Interrupts are
[When reading]
0: No mask setting
1: Mask setting
R/W
19
−
R
1
3
1
masked
REJ09B0256-0100
R/W
18
−
R
1
2
1
USBH
SSI1
R/W
R/W
17
1
1
1
SECU
RITY*
GETH
R/W
R/W
16
ER
1
0
1