r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 2013

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Numerics
0-Time PAUSE frame control ................ 981
10-Bit address format ........................... 1048
16-Bit timer pulse unit (TPU)................. 707
32-Bit address extended mode................ 177
7-Bit address format ............................. 1047
A
A/D converter ....................................... 1655
AC 97 Frame Slot Structure ................. 1409
Address space identifier (ASID)............. 145
Address translation ................................. 145
Addressing modes..................................... 59
Alarm function........................................ 780
Arithmetic operation instructions ............. 68
ASID....................................................... 156
Asynchronous Mode............................. 1151
Asynchronous serial communication
mode ..................................................... 1059
ATI ......................................................... 781
Audio Codec Interface (HAC).............. 1391
Automatic PAUSE frame
transmission ............................................ 980
Auto-Reload Count Operation ................ 701
Auto-Request mode ................................ 591
B
Baud rate generator............................... 1217
Baud Rate Generator for External
Clock (BRG)......................................... 1181
Big endian................................................. 52
Block diagram........................................... 13
Branch instructions ................................... 72
Break........................................... 1115, 1176
BRI ............................................. 1114, 1175
Index
Buffer operation ...................................... 734
Burst mode.............................................. 602
Bus Arbitration........................................ 405
C
Cacheability bit ....................................... 158
Caches..................................................... 187
CAM function ......................................... 969
Clock pulse generator (CPG) .................. 633
Clock valid reception ............................ 1017
Clock valid transmission....................... 1021
Clocked Synchronous Mode ................. 1152
Clocked synchronous serial
communication mode............................ 1059
Compare match timer (CMT) ................. 747
Control registers........................................ 39
Crystal Oscillator Circuit ........................ 781
CUI ......................................................... 781
Cycle-steal mode..................................... 600
D
D/A converter (DAC) ........................... 1673
Data address error ................................... 123
Data alignment ........................................ 412
Data TLB miss exception................ 118, 169
Data TLB multiple hit exception ............ 169
Data TLB multiple-hit exception ............ 117
Data TLB protection violation
exception......................................... 121, 170
DDR-SDRAM commands ...................... 432
DDR-SDRAM interface (DDRIF) .......... 409
Delay slot .................................................. 57
Delayed branches ...................................... 57
Descriptor and Transmit/Receive
Buffer ...................................................... 952
Rev. 1.00 Oct. 01, 2007 Page 1947 of 1956
REJ09B0256-0100