r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 646

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 14 Direct Memory Access Controller (DMAC)
Rev. 1.00 Oct. 01, 2007 Page 580 of 1956
REJ09B0256-0100
Bit
17
16
15, 14
Bit Name
AM
AL
DM[1:0]
Initial
Value
0
0
00
R/W
R/W
R/W
R/W
Descriptions
Acknowledge Mode
Selects whether DACK is output in data read cycle or in
data write cycle.
This bit is valid only in CHCR0 to CHCR3.
0: DACK output in read cycle
1: DACK output in write cycle
Acknowledge Level
Specifies whether the DACK signal output is high active
or low active.
This bit is valid only in CHCR0 to CHCR3.
0: Low-active output of DACK and TEND
1: High-active output of DACK and TEND
Destination Address Mode
Specify whether the DMA destination address is
incremented, decremented, or left fixed.
00: Fixed destination address
01: Destination address is incremented
10: Destination address is decremented
11: Setting prohibited
+1 in byte units transfer
+2 in word units transfer
+4 in longword units transfer
+16 in 16-byte units transfer
+32 in 32-byte units transfer
–1 in byte units transfer
–2 in word units transfer
–4 in longword units transfer
Setting prohibited in 16/32-byte units transfer