r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 906

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 23 Gigabit Ethernet Controller (GETHER)
23.3.28 Burst Cycle Count Upper-Limit Register (BCULR)
BCULR sets the upper limit for the number of burst cycles.
Rev. 1.00 Oct. 01, 2007 Page 840 of 1956
REJ09B0256-0100
Bit
31 to 12
11 to 0
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
Bit Name

BSTLMT[11:0] All 0
31
15


R
R
0
0
30
14


R
R
0
0
29
13


R
R
0
0
Initial
Value
All 0
28
12


R
R
0
0
R/W
27
11

R
0
0
R/W Description
R
R/W Burst Cycle Upper-Limit
R/W
26
10

R
0
0
Reserved
These bits are always read as 0. The write value should
always be 0.
These bits set the upper limit for burst cycles. Burst
transfer is finished when the burst timer exceeds the
value set in this register. If the burst timer exceeds the
value set in this register while a frame is being
transferred, burst transfer is continued until transfer of
the corresponding frame is completed.
H'000 to H'100: Burst cycle count is 256 cycles
H'101: Burst cycle count is 257 cycles
H'FFE: Burst cycle count is 4,094 cycles
H'FFF: Burst cycle count is 4,095 cycles
Note: 1 cycle = 32 ns
R/W
25

R
0
9
0
:
R/W
24

R
0
8
0
:
R/W
23

R
0
7
0
BSTLMT[11:0]
R/W
22

R
0
6
0
R/W
21

R
0
5
0
R/W
20

R
0
4
0
R/W
19

R
0
3
0
R/W
18

R
0
2
0
17

R
0
1
0
R/W
16

R
0
0
0