r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1831

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Notes: 1. If the data value is included in the match conditions, be sure to specify the operand
Bit
7, 6
5, 4
3
2, 1
0
2. If the quadword access is specified and the data value is included in the match
Bit Name
CD
ID
—
RW
CE
size.
conditions, the upper and lower 32 bits of 64-bit data are each compared with the
contents of both the match data setting register and the match data mask setting
register.
Initial
Value
All 0
All 0
0
All 0
0
R/W
R/W
R/W
R
R/W
R/W
Description
Bus Select
Specifies the bus to be included in the match conditions.
This bit is valid only when the operand access cycle is
specified as a match condition.
00: Operand bus for operand access
Others: Reserved (setting prohibited)
Instruction Fetch/Operand Access Select
Specifies the instruction fetch cycle or operand access
cycle as the match condition.
00: Instruction fetch cycle or operand access cycle
01: Instruction fetch cycle
10: Operand access cycle
11: Instruction fetch cycle or operand access cycle
Reserved
For read/write in this bit, refer to General Precautions on
Handling of Product.
Bus Command Select
Specifies the read/write cycle as the match condition.
This bit is valid only when the operand access cycle is
specified as a match condition.
00: Read cycle or write cycle
01: Read cycle
10: Write cycle
11: Read cycle or write cycle
Channel Enable
Validates/invalidates the channel. If this bit is 0, all the
other bits of this register are invalid.
0: Invalidates the channel.
1: Validates the channel.
Rev. 1.00 Oct. 01, 2007 Page 1765 of 1956
Section 41 User Break Controller (UBC)
REJ09B0256-0100