r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1107

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r5s77631ay266bgv

Manufacturer Part Number
r5s77631ay266bgv
Description
Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
26.3.8
26.3.9
Bit
7 to 1
0
Master Address Register (ICMAR)
Clock Control Register (ICCCR)
Bit Name
SADD1[6:0] All 0
STM1
Initial value:
Initial value:
R/W:
Initial Value
0
R/W:
BIt:
Bit:
R/W
R/W
7
0
7
0
R/W
R/W
6
0
6
0
R/W
R/W
R/W
R/W
R/W
SCGD[5:0]
5
0
5
0
SADD1[6:0]
R/W
R/W
4
0
Description
Slave Address
These bits are the address of the slave which
the master communicates with.
Slave Transfer Mode
This bit specifies the mode in which the slave
operates.
Bit STM1 sets the operating mode (transmit or
receive mode) of the slave, which is an
external slave device whose address matches
the slave address (SADD1) sent from the
master. The slave device is automatically set to
transmit/receive mode by hardware on
reception of the STM1 signal.
When this bit is set to 1, it indicates a read
operation, when this bit is cleared to 0, it
indicates a write operation.
4
0
R/W
R/W
3
0
3
0
Rev. 1.00 Oct. 01, 2007 Page 1041 of 1956
R/W
R/W
2
0
2
0
R/W
R/W
1
0
Section 26 I
1
0
CDF[1:0]
R/W
STM1
R/W
0
0
0
0
2
C Bus Interface (IIC)
REJ09B0256-0100

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