r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 628

Manufacturer Part Number

r5s77631ay266bgv

Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series

Manufacturer

Renesas Electronics Corporation.

Section 13 PCI Controller (PCIC)

When the PCIC is used in target mode and all the three conditions below are satisfied, data may be

lost during a PCIC target read.

1. PFCS bit in PCICR = 1 (32-byte pre-fetch enabled)

2. FTO bit in PCICR = 1 (TRDY control enabled)

3. PFE bit in PCICR = 1 (pre-fetch enabled)

For target reading in target mode, at least one of the above three conditions must be cancelled.

When the PCIC is used while all the five conditions below are satisfied, REQn (n = 3 to 1) with

the lowest priority is masked, thus disabling correct transfers via the PCI bus, which leads to

unstable operation of the PCI bus system.

1. Host mode (MD6 = high)

2. PCI bus master arbitration mode is set to fixed mode (BMAM bit in PCICR = 0)

3. In addition to this LSI (with the PCIC in host mode), two or more external PCI devices that

4. Among the above external devices, there is at least one device (REQm) that does not execute

5. There is an external device (REQn; n > m) that can be a bus master with a priority lower than

Rev. 1.00 Oct. 01, 2007 Page 562 of 1956

REJ09B0256-0100

Figure 13.27 Timing Example of Device (REQm) Not Executing REQ Negation and FRAME

can be a bus master are connected to the PCI bus.

REQ negation and FRAME assertion simultaneously when a single transaction is requested

(single or burst transfer).

the priority of the external device (REQm) satisfying condition 4 above.

Notes on PCIC Target Reading

Notes on Host Mode

Assertion Simultaneously