r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 632

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 14 Direct Memory Access Controller (DMAC)
• Active levels for both the DMA transfer request acceptance signal (DACKn) and DMA
Figure 14.1 shows the block diagram of the DMAC.
Rev. 1.00 Oct. 01, 2007 Page 566 of 1956
REJ09B0256-0100
On-chip memory
[Legend]
CHCRm:
DARBn:
DARm:
DMAE:
DMAOR :
m:
n:
Note:
Interrupt controller
External ROM
External RAM
transfer end signal (TENDn) can be set. (n = 0 to 3)
External I/O
peripheral
DREQ0 to DREQ3
DACK0 to DACK3
TEND0 to TEND3
On-chip
module
DMA transfer end signal
0,1,2,3,4,5 for channels 0 to 5
0,1,2,3 for channels 0 to 5
*
DMA transfer request signal
The half-end interrupt request is available in channels 0 to 3.
DMA channel control register
DMA destination address register B
DMA destination address register
DMA Address error interrupt request
DMA operation register
DMINT0 to DMINT5
DMAE
bus controller
Peripheral
Local bus state
DDR-SDRAM
PCI controller
controller
interface
Figure 14.1 Block Diagram of DMAC
DMARS0 to
DMARS2:
DMINTm:
SARBn:
SARm:
TCRBn:
TCRm:
DMAC channels 0 to 5
DMA extended resource selectors 0 to 2
DMA transfer end/half-end interrupt request from channel m*
DMA source address register B
DMA source address register
DMA transfer count register B
DMA transfer count register
interface
Register
Request
Iteration
Start-up
Bus
control
control
control
priority
control
DMARS0-2
DMAOR0
CHCRm
SARBn
DARBn
TCRBn
SARm
DARm
TCRm